Background Information

I know ZERO FPGA stuff or like hardware stuff. I want to, but I’m stupid af. I need to learn some kind of hardware description language so I decided to go through this verilog exercises site. This post is just going through the verilog basics.

Basics

Simple wire

Verilog wires are directional and flow in one direction, from source to sink. Verilog “continuous assignment” is assign left_side = right_side; as the value of the signal of the right is driven to the wire on the left. Ports have a direction (input or output). Input is driven by something from outside the module, while output drives something outside.

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module top_module( input in, output out );
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  assign out = in;
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endmodule

Four Wires

For multiple assign statements, order in which they appear does not matter. Assign statements describe connections between things, not copying values from one thing to another

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module top_module(
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    input a,b,c,
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    output w,x,y,z );
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  assign w = a;
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    assign x = b;
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    assign y = b;
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    assign z = c;
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endmodule

Inverter

An inverter is a NOT gate

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module top_module( input in, output out );
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 assign out = ~in;
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endmodule

AND gate

An AND gate has two inputs, and drives out the AND of the signals a and b. “driven” just means “has a known value by something attached to it”

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module top_module(
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    input a,
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    input b,
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    output out );
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  assign out = a & b;
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endmodule

NOR gate

NOR gate is an OR gate with its output inverted. NOR function needs two operators when written in verilog.

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module top_module( input a, input b, output out );
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    assign out = !(a | b);
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endmodule

XNOR gate

XNOR is just inverted XOR gate.

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assign out = !(a ^ b);

Declaring Wires

Need wires to connect internal components together. When need to use wire, should declare it in the body of the module, somewhere before it is used Basics use signal of type wire

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`default_nettype none
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module top_module(
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    input a,
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    input b,
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    input c,
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    input d,
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    output out,
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    output out_n   );
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    wire wireab = a & b;
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    wire wirecd = c & d;
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    wire wireabcd = !(wireab | wirecd);
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    assign out = !(wireabcd);
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    assign out_n = (wireabcd);
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endmodule

7458 chip

7458 is a chip with four AND and two OR gates.

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module top_module (
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    input p1a, p1b, p1c, p1d, p1e, p1f,
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    output p1y,
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    input p2a, p2b, p2c, p2d,
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    output p2y );
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    wire p1abc = (p1a & p1b & p1c);
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    wire p1fed = (p1f & p1e & p1d);
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    wire p2ab = (p2a & p2b);
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    wire p2cd = (p2c & p2d);
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    assign p1y = p1abc | p1fed;
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    assign p2y = p2ab | p2cd;
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endmodule

Vectors

Vectors

Vectors are used to group related signals using one name to make it more convenient to manipulate. For example, wire [7:0] w; declares an 8-bit vector named w that is functionally equivalent to having 8 separate wires. Notice that the declaration of a vector places the dimensions before the name of the vector, which is unusual compared to C syntax. However, the part select has the dimensions after the vector name as you would expect.

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module top_module (
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    input wire [2:0] vec,
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    output wire [2:0] outv,
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    output wire o2,
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    output wire o1,
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    output wire o0  ); // Module body starts after module declaration
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    assign o0 = vec[0];
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    assign o1 = vec[1];
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    assign o2 = vec[2];
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    assign outv = vec;
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endmodule

Vectors in more detail

tbc.